// 自定义
VA_BITS = 48
PA_BITS = 48

// 0xffff000000000000 => 内核空间起始(确保满足实际地址映射 + 0x40080000)
// + 2G => 内核空间结束, 上述地址 + 2G
//
// 0xffff001000000000 => 内核 io 空间起始
// + 16G
//
// 0xffff002000000000 => 内核线性内存空间起始
// + 16G -> 结束(16G 足够)

// [vaddr = 0xffff000040080000, paddr = 0x40080000, end = + 1G]
KIMAGE_VADDR   = 0xffff000040080000
// [vaddr = 0xffff001000000000, paddr = 0x0, end = + 16G]
KIO_VADDR      = 0xffff001000000000
KIO_VADDR_END  = 0xffff001400000000
// [vaddr = 0xffff002000000000, paddr = 0x0, end = + 16G]
KMEM_VADDR     = 0xffff002000000000
KMEM_VADDR_END = 0xffff002400000000
// [vaddr = 0xffff003000000000, paddr = 0x0, end = + 16G]
KPAGE_VADDR     = 0xffff003000000000
KPAGE_VADDR_END = 0xffff003400000000

// 硬件定义
CurrentEL_EL2 = (2 << 2)

SCTLR_EL1_RES1 = (1 << 11 | 1 << 20 | 1 << 22 | 1 << 28 | 1 << 29)
SCTLR_EL2_RES1 = (1 << 4 | 1 << 5 | 1 << 11 | 1 << 16 | 1 << 18 | 1 << 22 | 1 << 23 | 1 << 28 | 1 << 29)

// 小端
ENDIAN_SET_EL1 = 0
ENDIAN_SET_EL2 = 0

BOOT_CPU_MODE_EL1 = 0xe11   // boot 在 el1
BOOT_CPU_MODE_EL2 = 0xe12   // boot 在 el2

// SPSR bits
PSR_F_BIT = 0x00000040
PSR_I_BIT = 0x00000080
PSR_A_BIT = 0x00000100
PSR_D_BIT = 0x00000200

PSR_MODE_EL0t = 0x00000000
PSR_MODE_EL1t = 0x00000004
PSR_MODE_EL1h = 0x00000005
PSR_MODE_EL2t = 0x00000008
PSR_MODE_EL2h = 0x00000009
PSR_MODE_EL3t = 0x0000000c
PSR_MODE_EL3h = 0x0000000d
PSR_MODE_MASK = 0x0000000f

PSR_MODE32_BIT = 0x00000010

// 页表属性
MT_DEVICE_nGnRnE = 0
MT_DEVICE_nGnRE  = 1
MT_DEVICE_GRE    = 2
MT_NORMAL_NC     = 3
MT_NORMAL        = 4
MT_NORMAL_WT     = 5

// Memory region attributes for LPAE:
//
//  n = AttrIndx[2:0]
//      n   MAIR
//  DEVICE_nGnRnE   000	00000000
//  DEVICE_nGnRE    001	00000100
//  DEVICE_GRE      010	00001100
//  NORMAL_NC       011	01000100
//  NORMAL          100	11111111
//  NORMAL_WT       101	10111011
MAIR_ATTR = (0x04 << (MT_DEVICE_nGnRE * 8)) | (0x0c << (MT_DEVICE_GRE * 8)) | (0x44 << (MT_NORMAL_NC * 8)) | (0xff << (MT_NORMAL * 8)) | (0xbb << (MT_NORMAL_WT * 8))

PGD_TYPE_TABLE = 3 << 0

PUD_TYPE_SECT = (1 << 0)
PUD_TYPE_AF   = (1 << 10)
PUD_SECT_S    = (3 << 8)

SWAPPER_PUD_FLAGS = (PUD_TYPE_SECT | PUD_TYPE_AF |  PUD_SECT_S)

SWAPPER_MM_NORMALFLAGS = (MT_NORMAL << 2) | SWAPPER_PUD_FLAGS           // 默认的 mmu flags, 可读可写可执行
SWAPPER_MM_IOFLAGS     = (MT_DEVICE_nGnRE << 2) | SWAPPER_PUD_FLAGS     // 默认的 mmu flags, NC IO 读写

PGD_SHIFT = 39
PGD_SIZE  = 0x8000000000    // 512G
PGD_MASK  = 0xffffff8000000000
PTRS_PER_PGD = 512

PUD_SHIFT = 30
PUD_SIZE  = 0x40000000      // 1G
PUD_MASK  = 0xffffffffc0000000
PTRS_PER_PUD = 512

PMD_SHIFT = 21
PMD_SIZE  = 0x200000        // 2M
PMD_MASK  = 0xffffffffffe00000
PTRS_PER_PMD = 512

PTE_SHIFT = 12
PTE_SIZE  = 0x1000          // 4K
PTE_MASK  = 0xfffffffffffff000
PTRS_PER_PTE = 512

PAGE_SIZE = PTE_SIZE

// 通用的 SCTLR_ELx flags
SCTLR_ELx_DSSBS = (1 << 44)
SCTLR_ELx_ENIA  = (1 << 31)
SCTLR_ELx_ENIB  = (1 << 30)
SCTLR_ELx_ENDA  = (1 << 27)
SCTLR_ELx_EE    = (1 << 25)
SCTLR_ELx_IESB  = (1 << 21)
SCTLR_ELx_WXN   = (1 << 19)
SCTLR_ELx_ENDB  = (1 << 13)
SCTLR_ELx_I     = (1 << 12)
SCTLR_ELx_SA    = (1 << 3)
SCTLR_ELx_C     = (1 << 2)
SCTLR_ELx_A     = (1 << 1)
SCTLR_ELx_M     = (1 << 0)

// SCTLR_EL1 特定的 flags
SCTLR_EL1_UCI     = (1 << 26)
SCTLR_EL1_E0E     = (1 << 24)
SCTLR_EL1_SPAN    = (1 << 23)
SCTLR_EL1_NTWE	  = (1 << 18)
SCTLR_EL1_NTWI    = (1 << 16)
SCTLR_EL1_UCT     = (1 << 15)
SCTLR_EL1_DZE     = (1 << 14)
SCTLR_EL1_UMA     = (1 << 9)
SCTLR_EL1_SED     = (1 << 8)
SCTLR_EL1_ITD     = (1 << 7)
SCTLR_EL1_CP15BEN = (1 << 5)
SCTLR_EL1_SA0     = (1 << 4)

SCTLR_EL1_SET = (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | SCTLR_EL1_DZE  | SCTLR_EL1_UCT | SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_RES1)

TCR_T0SZ_OFFSET = 0
TCR_T1SZ_OFFSET = 16
TCR_T0SZ        = ((64 - VA_BITS) << TCR_T0SZ_OFFSET)
TCR_T1SZ        = ((64 - VA_BITS) << TCR_T1SZ_OFFSET)
TCR_TxSZ        = (TCR_T0SZ | TCR_T1SZ)
TCR_TxSZ_WIDTH  = 6

TCR_IRGN0_SHIFT = 8
TCR_IRGN1_SHIFT = 24
TCR_IRGN0_WBWA  = 1 << TCR_IRGN0_SHIFT
TCR_IRGN1_WBWA  = 1 << TCR_IRGN1_SHIFT
TCR_IRGN_WBWA   = (TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)

TCR_ORGN0_SHIFT = 10
TCR_ORGN1_SHIFT = 26
TCR_ORGN0_WBWA  = 1 << TCR_ORGN0_SHIFT
TCR_ORGN1_WBWA  = 1 << TCR_ORGN1_SHIFT
TCR_ORGN_WBWA   = (TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)

TCR_SH0_SHIFT = 12
TCR_SH1_SHIFT = 28
TCR_SH0_INNER = (3 << TCR_SH0_SHIFT)
TCR_SH1_INNER = (3 << TCR_SH1_SHIFT)
TCR_SHARED    = (TCR_SH0_INNER | TCR_SH1_INNER)

TCR_TG0_SHIFT = 14
TCR_TG1_SHIFT = 30
TCR_TG0_4K    = (0 << TCR_TG0_SHIFT)
TCR_TG1_4K    = (2 << TCR_TG1_SHIFT)

TCR_CACHE_FLAGS = (TCR_IRGN_WBWA | TCR_ORGN_WBWA)
TCR_SMP_FLAGS   = TCR_SHARED
TCR_TG_FLAGS    = (TCR_TG0_4K | TCR_TG1_4K)

TCR_A1          = (1 << 22)
TCR_ASID16		= (1 << 36)
TCR_TBI0        = (1 << 37)

ID_AA64MMFR0_PARANGE_48 = 0x5
ID_AA64MMFR0_PARANGE_MAX = ID_AA64MMFR0_PARANGE_48
ID_AA64MMFR0_PARANGE_SHIFT = 0
TCR_IPS_SHIFT = 32

ID_AA64MMFR0_TGRAN4_SHIFT     = 28
ID_AA64MMFR0_TGRAN4_SUPPORTED = 0
ID_AA64MMFR0_TGRAN_SHIFT     = ID_AA64MMFR0_TGRAN4_SHIFT
ID_AA64MMFR0_TGRAN_SUPPORTED = ID_AA64MMFR0_TGRAN4_SUPPORTED

KERNEL_DS = -1
USER_DS = ((1 << VA_BITS) - 1)

// 注意下面的值是从实际结构体中计算得来的, 因此如果相关结构体改变下面的值需要重新计算, 否则将会造成意料之外的错误!!!
S_LR = 0xf0
S_SP = 0xf8
S_PC = 0x100
S_PSTATE = 0x108
S_ORIG_X0 = 0x110
S_ORIG_ADDR_LIMIT = 0x120
S_STACKFRAME = 0x130
S_SYSCALLNO = 0x118
S_FRAME_SIZE = 0x140

TSK_STACK = 0x18
TSK_TI_ADDR_LIMIT = 0x20
TSK_TI_FLAGS = 0x28
TSK_TI_PREEMPT = 0x2c

NO_SYSCALL = -1

// 异常相关定义
BUG_BRK_IMM = 0x800

ESR_ELx_EC_SHIFT = 26

ESR_ELx_EC_UNKNOWN  = 0x00
ESR_ELx_EC_WFx      = 0x01
ESR_ELx_EC_FP_ASIMD = 0x07
ESR_ELx_EC_SVC64    = 0x15
ESR_ELx_EC_SYS64    = 0x18
ESR_ELx_EC_SVE      = 0x19
ESR_ELx_EC_IABT_LOW = 0x20
ESR_ELx_EC_IABT_CUR = 0x21
ESR_ELx_EC_PC_ALIGN = 0x22
ESR_ELx_EC_DABT_LOW = 0x24
ESR_ELx_EC_DABT_CUR = 0x25
ESR_ELx_EC_SP_ALIGN = 0x26
ESR_ELx_EC_FP_EXC64 = 0x2C
ESR_ELx_EC_BREAKPT_LOW = 0x30
ESR_ELx_EC_BREAKPT_CUR = 0x31
ESR_ELx_EC_BRK64       = 0x3C

// 线程 flags 定义
TIF_NEED_RESCHED = 1

_TIF_WORK_MASK = 1 << TIF_NEED_RESCHED
